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| DATA SHEET PD753204, 753206, 753208 4-BIT SINGLE-CHIP MICROCONTROLLERS MOS INTEGRATED CIRCUIT The PD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing capability comparable to that of an 8-bit microcontroller. The PD753208 has an on-chip LCD controller/driver and is based on the PD75308B of the 75X Series. However, the PD75308B is supplied in an 80-pin package, whereas the PD753208 is supplied in a 48pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In addition, the PD753208 features expanded CPU functions and performs high-speed operations at a low voltage of 1.8 V. Detailed information about functions can be found in the following user's manual. Be sure to read it before designing. PD753208 User's Manual: U10158E Features * Low-voltage operation: VDD = 1.8 to 5.5 V - Can be driven by two 1.5-V batteries * Internal memory - Program memory (ROM): 4096 x 8 bits (PD753204) 6144 x 8 bits (PD753206) 8192 x 8 bits (PD753208) - Data memory (RAM): 512 x 4 bits * Variable instruction execution time for high-speed operation and power saving operation - 0.95, 1.91, 3.81, 15.3 s (@ 4.19-MHz operation) - 0.67, 1.33, 2.67, 10.7 s (@ 6.0-MHz operation) * Internal programmable LCD controller/driver * Small package: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) * One-time PROM version: PD75P3216 Applications Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems, gas meters, etc. Ordering Information Part number Package 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) ROM (x 8 bits) 4096 6144 8192 PD753204GT-xxx PD753206GT-xxx PD753208GT-xxx Remark xxx indicates ROM code suffix. Unless otherwise specified, references in this data sheet to the PD753208 mean the PD753204 and the PD753206. The information in this document is subject to change without notice. Document No. U10166EJ2V0DS00 (2nd edition) Date Published March 1997 N Printed in Japan The mark shows major revised points. (c) 1996 PD753204, 753206, 753208 Function Outline Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (@ 4.19-MHz operation with system clock) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0-MHz operation with system clock) ROM 4096 x 8 bits (PD753204) 6144 x 8 bits (PD753206) 8192 x 8 bits (PD753208) RAM General-purpose register 512 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 6 20 Connecting on-chip pull-up resistors can be specified by software: 5 Connecting on-chip pull-up resistors can be specified by software: 20 Also used for segment pins: 8 On-chip pull-up resistors can be specified by mask option 13-V withstand voltage Internal memory Input/ output port CMOS input CMOS input/output N-ch open-drain input/output Total LCD controller/driver 4 30 * Segment selection: * Display mode selection: 4/8/12 segments (can be changed to CMOS input/ output port in 4-time units; max. 8) Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) * On-chip split resistor for LCD drive can be specified by mask option Timer 5 channels * 8-bit timer/event counter: 1 channel * 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier generator, and timer with gate) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode 16 bits * , 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock) * , 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock) * 2, 4, 32 kHz (@ 4.19-MHz operation with system clock) * 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock) External: 2, Internal: 5 External: 1, Internal: 1 Ceramic or crystal oscillator for system clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) Serial interface Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ) Vectored interrupts Test input System clock oscillator Standby function Power supply voltage Package 2 PD753204, 753206, 753208 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) .................................................................................................... 5 2. BLOCK DIAGRAM ................................................................................................................................ 6 3. PIN FUNCTIONS .................................................................................................................................... 7 3.1 Port Pins ......................................................................................................................................7 3.2 Non-Port Pins .............................................................................................................................. 9 3.3 Pin Input/Output Circuits ......................................................................................................... 11 3.4 Recommended Connections for Unused Pins ....................................................................... 13 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 14 4.1 Difference Between Mk I and Mk II Modes .............................................................................. 14 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 15 5. MEMORY CONFIGURATION ............................................................................................................. 16 6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 21 6.1 Digital I/O Port ........................................................................................................................... 21 6.2 Clock Generator ........................................................................................................................ 22 6.3 Clock Output Circuit ................................................................................................................. 23 6.4 Basic Interval Timer/Watchdog Timer ..................................................................................... 24 6.5 Watch Timer .............................................................................................................................. 25 6.6 Timer/Event Counter ................................................................................................................. 26 6.7 Serial Interface .......................................................................................................................... 30 6.8 LCD Controller/Driver ............................................................................................................... 32 6.9 Bit Sequential Buffer ................................................................................................................ 34 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 35 8. STANDBY FUNCTION ........................................................................................................................ 37 9. RESET FUNCTION ............................................................................................................................. 38 10. MASK OPTION ................................................................................................................................... 41 11. INSTRUCTION SET ............................................................................................................................ 42 12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 56 13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................... 68 14. PACKAGE DRAWINGS ..................................................................................................................... 70 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 71 3 PD753204, 753206, 753208 APPENDIX A PD753108, 753208, AND 75P3216 FUNCTIONAL LIST ............................................. 72 APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 74 APPENDIX C RELATED DOCUMENTS ................................................................................................ 77 4 PD753204, 753206, 753208 1. PIN CONFIGURATION (TOP VIEW) * 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) PD753204GT-xxx, PD753206GT-xxx, PD753208GT-xxx COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P30/LCDCL P31/SYNC P32 P33 VSS P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 VDD X1 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 S12 S13 S14 S15 P93/S16 P92/S17 P91/S18 P90/S19 P83/S20 P82/S21 P81/S22 P80/S23 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P10/INT0 P03/SI/SB1 P02/SO/SB0 P01/SCK P00/INT4 RESET IC Note Note Connect IC (Internally Connected) pin directly to VDD. Pin Identification P00 to P03 P10, P13 P20 to P23 P30 to P33 P50 to P53 P60 to P63 P80 to P83 P90 to P93 KR0 to KR3 COM0 to COM3 SCK SI SO SB0, SB1 : : : : : : : : : : : : : : Port0 Port1 Port2 Port3 Port5 Port6 Port8 Port9 Key Return 0 to 3 Common Output 0 to 3 Serial Clock Serial Input Serial Output Serial Data Bus 0, 1 S12 to S23 : VLC0 to VLC2 : BIAS : LCDCL : SYNC : TI0 : PTO0 to PTO2 : BUZ : PCL : INT0, INT4 : X1, X2 : RESET : IC : VDD : VSS : Segment Output 12 to 23 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 Programmable Timer Output 0 to 2 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 4 System Clock Oscillation 1, 2 Reset Internally Connected Positive Power Supply Ground 5 PD753204, 753206, 753208 2. BLOCK DIAGRAM BUZ/P23 WATCH TIMER INTW fLCD PORT0 PORT1 PORT2 PROGRAM COUNTER ALU CY SP (8) PORT3 SBS PORT5 BANK PORT6 PORT8 PORT9 PROGRAM Note MEMORY (ROM) DECODE AND CONTROL 4 2 4 4 4 4 4 4 P00 to P03 P10,P13 P20 to P23 P30 to P33 P50 to P53 P60 to P63 P80 to P83 P90 to P93 BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT TI0/P13 TPO0/P20 8-BIT TIMER/EVENT COUNTER #0 INTT0 TOUT INTT1 8-BIT TIMER CASCADED COUNTER #1 16-BIT TIMER 8-BIT COUNTER TIMER COUNTER #2 INTT2 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT INT0/P10 INT4/P00 KR0/P60 to KR3/P63 4 INTERRUPT CONTROL GENERAL REG. PTO1/P21 TOUT PTO2/PCL/P22 DATA MEMORY (RAM) 512 x 4 BITS 4 4 4 LCD CONTROLLER/ DRIVER 4 S12 to S15 S16/P93 to S19/P90 S20/P83 to S23/P80 COM0 to COM3 VLC0 VLC1 VLC2 BIAS LCDCL/P30 SYNC/P31 fX/2N CLOCK OUTPUT CONTROL CLOCK DIVIDER CPU CLOCK SYSTEM CLOCK GENERATOR STANDBY CONTROL fLCD BIT SEQ BUFFER (16) PCL/PTO2/P22 X1 X2 IC VDD VSS RESET Note The ROM capacity depends on the product. 6 PD753204, 753206, 753208 3. PIN FUNCTION 3.1 Port Pins (1/2) Alternate Function INT4 SCK SO/SB0 SI/SB1 INT0 Input port in 1 bit unit (PORT1). On-chip pull-up resistors can be specified by software in 2-bit units. Noise elimination circuit can be specified with P10/INT0. 4-bit input/output port (PORT2). On-chip pull-up resistors can be specified by software in 4-bit units. No Input 8-bit I/O Circuit After Reset I/O TYPE Note 1 No Input (B) (F)-A (F)-B (M)-C (B)-C Pin Name P00 P01 P02 P03 P10 Input/Output Input Input/Output Input/Output Input/Output Input Function 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistors can be specified by software in 3-bit units. P13 TI0 P20 P21 P22 P23 P30 P31 P32 P33 P50 to P53 Note 2 Input/Output PTO0 PTO1 PCL/PTO2 BUZ No Input E-B Input/Output LCDCL SYNC - - Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units. No Input E-B Input/Output - N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. No High level (when pullup resistors are provided) or highimpedance M-D Notes 1. Characters in parentheses indicate the Schmitt-trigger input. 2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. 7 PD753204, 753206, 753208 3.1 Port Pins (2/2) Alternate Function KR0 KR1 KR2 KR3 Input/Output S23 S22 S21 S20 Input/Output S19 S18 S17 S16 4-bit input/output port (PORT9). On-chip pull-up resistors can be specified by software in 4-bit units. Note 2 Input H 8-bit I/O Circuit After Reset I/O TYPE Note 1 No Input (F)-A Pin Name P60 P61 P62 P63 P80 P81 P82 P83 P90 P91 P92 P93 Input/Output Input/Output Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bitwise. On-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT8). On-chip pull-up resistors can be specified by software in 4-bit units. Note 2 Yes Input H Notes 1. Characters in parentheses indicate the Schmitt-trigger input. 2. Do not connect on-chip pull-up resistors specified by software when using as segment signal output pins. 8 PD753204, 753206, 753208 3.2 Non-Port Pins (1/2) Alternate Function P13 I/O Circuit TYPE Note 1 (B)-C Pin Name TI0 Input/Output Input Function Inputs external event pulses to the timer/event counter. Timer/event counter output Timer counter output After Reset Input PTO0 PTO1 PTO2 PCL BUZ Output P20 P21 P22/PCL P22/PTO2 P23 Input E-B Clock output Optional frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial data bus input/output Serial data input Serial data bus input/output Edge detection vectored interrupt input (both rising edge and falling edge detection) Edge detection vectored interrupt input (detection edge can be selected). Noise elimination circuit can be specified. With clock elimination circuit/asynchronous selectable Input Input (F)-A (F)-B SCK SO/SB0 Input/Output P01 P02 SI/SB1 P03 (M)-C INT4 Input P00 (B) INT0 Input P10 Input (B)-C KR0 to KR3 S12 to S15 S16 to S19 S20 to S23 COM0 to COM3 VLC0 to VLC2 Input/Output Output Output Output Output - P60 to P63 - P93 to P90 P83 to P80 - - Falling edge detection testable input Segment signal output Segment signal output Segment signal output Common signal output LCD drive power On-chip split resistor is enable (mask option). Output for external split resistor disconnect Clock output for externally expanded driver Clock output for externally expanded driver sync Input Note 2 Input Input Note 2 - (F)-A G-A H H G-B - BIAS LCDCL Note 4 SYNC Note 4 Output Input/Output Input/Output - P30 P31 Note 3 Input Input - E-B E-B Notes 1. Characters in parentheses indicate the Schmitt trigger input. 2. Each display output selects the following VLCX as input source. S12 to S15: VLC1, COM0 to COM2: VLC2, COM3: VLC0. 3. When a split resistor is contained ....... Low level When no split resistor is contained ...... High-impedance 4. These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. 9 PD753204, 753206, 753208 3.2 Non-Port Pins (2/2) Alternate Function - I/O Circuit TYPE Note 1 - Pin Name X1 Input/Output Input Function Crystal/ceramic connection pin for the system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. System reset input (low-level active) Internally connected. Connect directly to VDD. Positive power supply Ground potential After Reset - X2 - RESET IC VDD VSS Input - - - - - - - - - - - (B) - - - Note Characters in parentheses indicate the Schmitt-trigger input. 10 PD753204, 753206, 753208 3.3 Pin Input/Output Circuits The PD753208 pin input/output circuits are shown schematically. (1/2) TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT CMOS specification input buffer. TYPE B Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable data Type D output disable P-ch IN IN/OUT Schmitt trigger input having hysteresis characteristic. Type A P.U.R. : Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable data output disable IN Type B Type D P.U.R. P-ch P-ch IN/OUT P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor 11 PD753204, 753206, 753208 (2/2) TYPE F-B VDD P.U.R P.U.R enable output disable (P) data output disable output disable (N) N-ch data output disable TYPE E-B VDD P-ch IN/OUT P-ch SEG data TYPE G-A P-ch N-ch IN/OUT TYPE H P.U.R : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 VLC1 P-ch N-ch P-ch N-ch P-ch N-ch data OUT SEG data VLC2 P-ch N-ch N-ch P.U.R : Pull-Up Resistor N-ch output disable P.U.R. enable P.U.R P-ch IN/OUT N-ch TYPE G-B TYPE M-D VDD VLC0 P-ch N-ch data P-ch N-ch output disable input instruction VDD P.U.R. (Mask Option) IN/OUT VLC1 N-ch (+13-V withstand) P-ch P.U.R. Note OUT COM data N-ch VLC2 N-ch P-ch N-ch P-ch Voltage control circuit P.U.R. : Pull-Up Resistor Note Pull-up resistor that only operates upon the execution of an input instruction when the pull-up resistor is not connected via the mask option (it is available during low-voltage). 12 PD753204, 753206, 753208 3.4 Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL/PTO2 P23/BUZ P30/LCDCL P31/SYNC P32 P33 P50 to P53 Input state : Connect to VSS Output state : Connect to VSS (Do not connect pull-up resistor in the mask option) P60/KR0 to P63/KR3 : Connect individually to VSS or VDD via a resistor Output state : No connection No connection Input state Input state: Connect individually to VSS or VDD via a resistor Output state: No connection Connect to VSS Connect to VSS or VDD Recommended Connection Connect to VSS or VDD Connect individually to VSS or VDD via a resistor S0 to S15 COM0 to COM3 S16/P93 to S19/P90 S20/P83 to S23/P80 VLC0 to VLC2 BIAS Input state: Connect individually to VSS or VDD via a resistor Output state: No connection Connect to VSS Only if all of VLC0 to VLC2 are unused, connect to VSS. In other cases, no connection. Connect to VDD directly IC 13 PD753204, 753206, 753208 4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference Between Mk I and Mk II Modes The CPU of the PD753208 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the Stack Bank Select register (SBS). * Mk I mode: * Mk II mode: Upward compatible with the PD75308B. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. Incompatible with PD75308B. Can be used in all the 75XL CPU including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Number of stack bytes for subroutine instructions BRA ! addr1 instruction CALLA ! addr1 instruction CALL ! addr instruction CALLF ! faddr instruction 2 bytes 3 bytes Mk II mode Not available Available 3 machine cycles 2 machine cycles 4 machine cycles 3 machine cycles Caution The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Software compatibility with products whose program memory exceeds 16 Kbytes can be raised by using this mode. When the MkII mode is selected, the number of stack bytes increases by one byte per stack during subroutine call instruction execution compared with the MkI mode. When the !faddr instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore, if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI mode is recommended. 14 PD753204, 753206, 753208 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100xB Note at the beginning of a program. When using the Mk II mode, it must be initialized to 000xB Note. Note The desired numbers must be set in the x positions. Figure 4-1. Stack Bank Select Register Format Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS SBS2 SBS1 Stack area specification 0 0 0 1 Memory bank 0 Memory bank 1 Setting prohibited Other than above 0 0 must be set in the bit 2 position. Mode switching specification 0 1 Mk II mode Mk I mode Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. 15 PD753204, 753206, 753208 5. MEMORY CONFIGURATION * Program Memory (ROM) .... 4096 x 8 bits (PD753204) .... 6144 x 8 bits (PD753206) .... 8192 x 8 bits (PD753208) - Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. - Addresses 0002H to 000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can be started at an arbitrary address. - Addresses 0020H to 007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. * Data Memory (RAM) - Data area ... 512 words x 4 bits (000H to 1FFH) - Peripheral hardware area ... 128 words x 4 bits (F80H to FFFH) 16 PD753204, 753206, 753208 Figure 5-1. Program Memory Map (1/3) (a) PD753204 Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 2 H MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 0 4 H MBE RBE 0 0 INT0 INT0 006H start address start address start address start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instructions CALL !addr instruction subroutine entry address 0 0 0 H MBE RBE 0 0 8 H MBE RBE 0 0 INTCSI INTCSI start address start address start address start address start address start address (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) 0 0 A H MBE RBE 0 0 INTT0 INTT0 BR $addr instruction relative branch address -15 to -1, +2 to +16 0 0 C H MBE RBE 0 0 INTT1/INTT2 INTT1/INTT2 BRCB ! caddr instruction branch address 020H GETI instruction reference table 07FH 080H Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 17 PD753204, 753206, 753208 Figure 5-1. Program Memory Map (2/3) (b) PD753206 Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0006H start address start address start address start address 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR ! addr, BRA ! addr1Note or CALLA ! addr1Note instructions CALL ! addr instruction subroutine entry address BR $ addr instruction relative branch address -15 to -1, +2 to +16 0 0 0 0 H MBE RBE 0 0 0 8 H MBE RBE 0 INTCSI INTCSI start address start address start address start address start address start address (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1/INTT2 INTT1/INTT2 0020H GETI instruction reference table 007FH 0080H BRCB ! caddr instruction branch address Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 17FFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 18 PD753204, 753206, 753208 Figure 5-1. Program Memory Map (3/3) (c) PD753208 Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0006H start address start address start address start address 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR ! addr, BRA ! addr1Note or CALLA ! addr1Note instructions CALL ! addr instruction subroutine entry address BR $ addr instruction relative branch address -15 to -1, +2 to +16 0 0 0 0 H MBE RBE 0 0 0 8 H MBE RBE 0 INTCSI INTCSI start address start address start address start address start address start address (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1/INTT2 INTT1/INTT2 BRCB ! caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1FFFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 19 PD753204, 753206, 753208 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H 0 256 x 4 (224 x 4) Stack area Note Data area static RAM (512x4) 0FFH 100H 256 x 4 (236 x 4) 1 1EBH 1ECH 1F7H 1F8H 1FFH (32 x 4) Memory bank Display data memory area (12 x 4) (8 x 4) Not incorporated F80H Peripheral hardware area 128 x 4 15 FFFH Note As a stack area, either memory bank 0 or 1 can be selected. 20 PD753204, 753206, 753208 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port There are three kinds of I/O ports. * * * CMOS input ports (Ports 0, 1) CMOS input/output ports (Ports 2, 3, 6, 8, 9) N-ch open-drain input/output ports (Port 5) Total :6 : 20 :4 30 Table 6-1. Types and Features of Digital Ports Port PORT0 Function 4-bit input Operation and features The alternate function pins have an output function with operation mode when using the serial interface function. 2-bit input dedicated port Remarks Also used for the INT4, SCK, SO/SB0, and SI/SB1 pins. PORT1 1-bit input Also used for the INT0 and TI0. Also used for the PTO0 to PTO2, PCL, and BUZ pins. Also used for the LCDCL and SYNC pins. -- PORT2 4-bit I/O Can be set to input mode or output mode in 4-bit units. Can be set to input mode or output mode bit-wise. PORT3 PORT5 4-bit I/O (Nchannel opendrain, 13-V withstand) 4-bit I/O Can be set to input mode or output mode in 4-bit units. On-chip pull-up resistor can be specified by mask option bit-wise. PORT6 Can be set to input mode or output mode bit-wise. Also used for the KR0 to KR3 pins. Also used for the S20 to S23 pins. Also used for the S16 to S19 pins. PORT8 Can be set to input mode or output mode in 4-bit units. Ports 8 and 9 are paired and data can be input/ output in 8-bit units. PORT9 21 PD753204, 753206, 753208 6.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generator is determined by the Processor Clock Control Register (PCC). The instruction execution time can also be changed. * 0.95, 1.91, 3.81, 15.3 s (system clock: @ 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (system clock: @ 6.0-MHz operation) Figure 6-1. Clock Generator Block Diagram X1 VDD System clock oscillator X2 fX 1/1 to 1/4096 Divider 1/2 1/4 1/16 Oscillation stop Divider Selector 1/4 PCC PCC0 Internal bus PCC1 4 HALTNote STOPNote * Basic interval timer (BT) * Timer/event counter 0 * Timer counter 1, 2 * Watch timer * LCD controller/driver * Serial interface * INT0 noise eliminator * Clock output circuit * CPU * INT0 noise eliminator * Clock output circuit HALT F/F PCC2 PCC3 S R Q PCC2, PCC3 Clear STOP F/F Q S Wait release signal from BT RESET Signal R Standby release signal from interrupt control circuit Note Instruction execution 22 PD753204, 753206, 753208 Remarks 1. fX = System clock frequency 2. = CPU clock 3. PCC: Processor Clock Control Register 4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. 6.3 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2) to the remote control wave outputs and peripheral LSIs. * Clock Output (PCL) : , 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation) , 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation) Figure 6-2. Clock Output Circuit Block Diagram From clock generator fX/23 Selector fX/24 fX/26 From timer counter (channel 2) Selector Output buffer PCL/PTO2/P22 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 23 PD753204, 753206, 753208 6.4 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. * Interval timer operation to generate a reference time interrupt * Watchdog timer operation to detect program runaway and reset the CPU * Selects and counts the wait time when the standby mode is released * Reads the contents of counting Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear Basic interval timer (8-bit frequency divider) Set BT interrupt request flag Vectored interrupt IRQBT request signal Wait release signal when standby is released. Internal reset signal WDTM SET1Note 1 BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 8 Internal bus Note Instruction execution 24 PD753204, 753206, 753208 6.5 Watch Timer The PD753208 has one watch timer channel, whose functions are as follows. * Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. * 0.5 sec interval can be created with the system clock (4.194304 MHz) * Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. * Outputs a frequency (2.048, 4.096, or 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming of system clock frequencies. * Clears the frequency divider to make the clock start with zero seconds. Figure 6-4. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 (32.768 kHz) Selector fLCD From clock generator fW (32.768 kHz) 4 kHz 2 kHz fW fW 23 24 Divider fW 214 2 Hz 0.5 sec Selector INTW IRQW set signal Clear Selector Output buffer P23/BUZ WM Note 1 Note 2 PORT2.3 0 WM5 WM4 WM3 WM2 WM1 WM0 P23 output-latch PMGB bit 2 Port 2 input/ output mode WM7 8 Internal bus Notes 1. WM3 is undefined while reading data. 2. Be sure to set WM0 to 0. Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz. 25 PD753204, 753206, 753208 6.6 Timer/Event Counter The PD753208 provides one channel for timer/event counters and two channels for timer counters. Figures 6-5 to 6-7 show the block diagrams. Timer/event counter functions are as follows. * Programmable interval timer operation * Square wave output of any frequency to the PTO0 pin (n = 0 to 2). * Event counter operation (Channel 0 only) * Divides the frequency of signal input via the TI0 pin to 1-nth of the original signal and outputs the divided frequency to the PTO0 pin (frequency divider operation). * Supplies the shift clock to the serial interface circuit. * Reads the counting status. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Mode 8-bit timer/event counter mode Note 1 Gate control function PWM pulse generator mode 16-bit timer counter mode Gate control function Carrier generator mode A N/A Note 2 Channel 2 A N/A N/A A A A A A A N/A N/A N/ANote 2 N/A Notes 1. Channel 0 only. 8-bit timer counter mode for channel 1 and channel 2 2. Used for gate control signal generation Remark A: N/A: Available Not available 26 Figure 6-5. Timer/Event Counter Block Diagram (channel 0) Internal bus 8 TM0 - - Modulo register (8) T0 enable flag TMOD0 TOE0 SET1 8 8 Note - TM06 TM05 TM04 TM03 TM02 P20 output latch PORT2.0 PMGB bit 2 Port 2 input/output mode To serial interface TOUT0 PORT1.3 Comparator (8) 8 Match TOUT F/F 8 PTO0/P20 Output buffer Reset Input buffer T0 MPX CP Clear Count register (8) TI0/P13 fX/24 From fX/2 clock fX/28 generator fX/210 Timer operation start 6 INTT0 IRQT0 set signal RESET IRQT0 clear signal To timer counter (channel 2) Note Execution of instruction PD753204, 753206, 753208 Caution When data is set to TM0, always set bit 1 to 0. 27 28 Figure 6-6. Timer/Event Counter Block Diagram (channel 1) Internal bus 8 SET1 TM1 8 TMOD1 Decoder Modulo register (8) 8 Comparator (8) 8 T1 CP Clear Count register (8) Reset Match TOUT F/F P21/PTO1 Output buffer T1 enable flag P21 output latch TOE1 PORT2.1 Note PMGB bit 2 - TM16 TM15 TM14 TM13 TM12 TM11 TM10 Port 2 input/output mode Timer counter (channel 2) output fX/25 fX/26 From clock fX/28 generator fX/210 fX/212 MPX RESET Timer operation start 16 bit timer counter mode Selector IRQT1 clear signal Timer counter match signal (channel 2) (During 16-bit timer counter mode) Timer counter reload signal (channel 2) Timer counter comparator (channel 2) (During 16-bit timer counter mode) INTT1 IRQT1 set signal PD753204, 753206, 753208 Note Execution of instruction Figure 6-7. Timer Counter Block Diagram (channel 2) Internal bus 8 TMOD2H TM2 High-level period setting modulo register (8) TOE2 REMC NRZB NRZ Reload 8 8 8 TC2 SET1Note TM26 TM25 TM24 TM23 TM22 TM21 TM20 TMOD2 Modulo register (8) TGCE 8 8 MPX (8) 8 Match PORT2.2 PMGB bit 2 P22 Port 2 output latch input/output P22/PCL/PTO2 Output buffer Selector Decoder Comparator (8) 8 Reset TOUT F/F Overflow Carrier generator mode From clock generator CP Clear fX/2 fX/22 fX/24 fX/26 fX/28 fX/210 T2 Count register (8) 16-bit timer counter mode Timer operation start MPX Selector Selector Timer clock input (channel 1) INTT2 IRQT2 set signal IRQT2 clear signal RESET Timer event counter TOUT F/F (channel 0) Timer counter clear signal (channel 1) (During 16-bit timer counter mode) Timer counter match signal (channel 1) (During 16-bit timer counter mode) From clock generator Timer counter match signal (channel 1) (When carrier generator mode) PD753204, 753206, 753208 Note Execution of instruction 29 PD753204, 753206, 753208 6.7 Serial Interface The PD753208 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four modes. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode (serial bus interface mode) 30 Figure 6-8. Serial Interface Block Diagram Internal bus 8/4 8 CSIM Match signal RELT CMDT (8) SO latch SET CLR Selector Shift register (SIO) D (8) ACKT ACKE BSYE Q Address comparator Slave address register (SVA) (8) SBIC 8 Bit test 8 Bit manipulation Bit test P03/SI/SB1 P02/SO/SB0 Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD Busy/ acknowledge output circuit P01/SCK Serial clock counter INTCSI INTCSI control circuit IRQCSI set signal P01 output Iatch Serial clock control circuit Serial clock selector fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel 0)) External SCK PD753204, 753206, 753208 31 PD753204, 753206, 753208 6.8 LCD Controller/Driver The PD753208 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the panel directly. The PD753208 LCD controller/driver functions are as follows: * Display data memory is read automatically by DMA operation and segment and common signals are generated. * Display mode can be selected from among the following five: <1> <2> <3> <4> <5> Static 1/2 duty (time multiplexing by 2), 1/2 bias 1/3 duty (time multiplexing by 3), 1/2 bias 1/3 duty (time multiplexing by 3), 1/3 bias 1/4 duty (time multiplexing by 4), 1/3 bias * A frame frequency can be selected from among four in each display mode. * A maximum of 12 segment signal output pins (S12 to S23) and four common signal output pins (COM0 to COM3). * The segment signal output pins (S16 to S23) can be changed to the I/O ports (PORT8 and PORT9). * Split-resistor can be incorporated to supply LCD drive power. (Mask option) - - Various bias methods and LCD drive voltages can be applicable. When display is off, current flowing through the split resistor is cut. * Display data memory not used for display can be used for normal data memory. 32 Figure 6-9. LCD Controller/Driver Block Diagram Internal bus 8 1F7H Display mode register 3210 3210 3210 3210 LCD/port selection register 1F0H 1EFH 1ECH 4 4 8 4 Display control register 4 Port 3 output latch 10 4 Port mode register group A 4 4 4 4 Port 8 output latch 3210 Port 9 Port mode output latch register group C 3210 0 1 1 0 Decoder 3210 3210 3210 3210 Timing controller fLCD Port 8 Input/Output buffer 01 2 3 Segment driver Port 9 Input/Output buffer 01 2 3 Segment driver Common driver LCD drive voltage control LCD drive mode switching PD753204, 753206, 753208 S23/P80 S16/P93 S15 S0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 P31/SYNC P30/LCDCL 33 PD753204, 753206, 753208 6.9 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. Figure 6-10. Bit Sequential Buffer Format Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L = FH L = CH L = BH L = 8H L = 7H L = 4H L = 3H DECS L L = 0H INCS L Remarks 1. In pmem.@L addressing, the specified bit moves corresponding to the L register. 2. In pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification. 34 PD753204, 753206, 753208 7. INTERRUPT FUNCTION AND TEST FUNCTION There are seven interrupt sources and two test sources in the PD753208. The interrupt control circuit of the PD753208 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQxxx) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag. 35 36 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 4 IME IPS IM0 Decoder INTBT VRQn 2 IST1 IST0 Interruput enable flag (IExxx) IM2 IRQBT IRQ4 IRQ0 IRQCSI IRQT0 IRQT1 IRQT2 IRQW IRQ2 Priority control circuit INT4/P00 INT0/P10 INTCSI INTT0 INTT1 INTT2 INTW Selector Note Selector Both edge detector Edge detector Vector table address generator KR0/P60 KR3/P63 Falling edge detector Standby release signal IM2 PD753204, 753206, 753208 Note Noise eliminator (Standby release is disabled when noise eliminator is selected.) PD753204, 753206, 753208 8. STANDBY FUNCTION In order to save power dissipation while a program is in standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD753208. Table 8-1. Operation Status in Standby Mode Item Set instruction Operation status Clock generator Mode STOP mode STOP instruction The system clock stops oscillation. HALT mode HALT instruction Only the CPU clock halts (oscillation continues). Operable only when the system clock is oscillated. (The IRQBT is set in the reference interval). Operable Basic interval timer/ Watchdog timer Operation stops. Serial interface Operable only when an external SCK input is selected as the serial clock. Operable only when a signal input to the TI0 pin is specified as the count clock. Operation stops. Operation stops. The INT4 is operable. Only the INT0 is not operated Operation stops. Timer/event counter Operable Watch timer LCD controller/driver External interrupt Operable Operable Note . CPU Release signal Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or RESET signal input. Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 37 PD753204, 753206, 753208 9. RESET FUNCTION There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/ watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal RESET signal RESET signal sent from the basic interval timer/watchdog timer WDTM Internal bus Each hardware is initialized by the RESET signal generation as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms: @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation) 2 15/fX (5.46 ms: @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation) 38 PD753204, 753206, 753208 Table 9-1. Status of Each Device After Reset (1/2) RESET signal generation in the standby mode RESET signal generation during operation Sets the low-order 4 bits of program memory's address 0000H to PC11 to PC8 and the contents of address 0001H to PC7 to PC0. Sets the low-order 5 bits of program memory's address 0000H to PC12 to PC8 and the contents of address 0001H to PC7 to PC0. Undefined 0 0 Sets bit 6 of program memory's address 0000H to RBE and bit 7 to MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH Hardware Program counter (PC) PD753204 Sets the low-order 4 bits of program memory's address 0000H to PC11 to PC8 and the contents of address 0001H to PC7 to PC0. PD753206, Sets the low-order 5 bits of PD753208 program memory's address 0000H to PC12 to PC8 and the contents of address 0001H to PC7 to PC0. PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Held 0 0 Sets bit 6 of program memory's address 0000H to RBE and bit 7 to MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer counter (T2) Counter (T2) Modulo register (TMOD2) High-level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB TGCE Watch timer Mode register (WM) 0 0, 0 0, 0, 0 0 0 0 0, 0 0, 0, 0 0 0 39 PD753204, 753206, 753208 Table 9-1. Status of Each Device After Reset (2/2) RESET signal generation in the standby mode Held 0 0 Held 0 0 0 0 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 0 Held RESET signal generation during operation Undefined 0 0 Undefined 0 0 0 0 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 0 Undefined Hardware Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit LCD controller/ driver Processor clock control register (PCC) Clock output mode register (CLOM) Display mode register (LCDM) Display control register (LCDC) LCD/port selection register (LPS) Interrupt function Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt priority selection register (IPS) INT0, 2 mode registers (IM0, IM2) Digital port Output buffer Output latch I/O mode registers (PMGA, B, C) Pull-up resistor setting register (POGA, B) Bit sequential buffer (BSB0 to BSB3) 40 PD753204, 753206, 753208 10. MASK OPTION The PD753208 has the following mask options. * P50 to P53 mask options Selects whether or not to connect an internal pull-up resistor. <1> Connect pull-up resistor internally bit-wise. <2> Do not connect pull-up resistor internally. * VLC0 to VLC2 pins, BIAS pins mask option Selects whether or not to internally connect LCD-driving split resistors. <1> Do not connect split resistor internally. <2> Connect four 10-k (typ.) split resistors simultaneously internally. <3> Connect four 100-k (typ.) split resistors simultaneously internally. * Standby function mask option Selects the wait time with the RESET signal. <1> 2 17/fx (21.8 ms: When fX = 6.0 MHz, 31.3 ms: When fX = 4.19 MHz) <2> 2 15/fx (5.46 ms: When fX = 6.0 MHz, 7.81 ms: When fX = 4.19 MHz) 41 PD753204, 753206, 753208 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER PACKAGE USERS' MANUAL--LANGUAGE (EEU-1363)". If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see the user's manual. Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, BC, XA, BC, BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Description method HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label Note FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 000H-FFFH immediate data or label (PD753204) 0000H-17FFH immediate data or label (PD753206) 0000H-1FFFH immediate data or label (PD753208) 000H-FFFH immediate data or label (PD753204) 0000H-17FFH immediate data or label (PD753206) 0000H-1FFFH immediate data or label (PD753208) 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit 0 = 0) or label PORT0-PORT3, PORT5, PORT6, PORT8, PORT9 IEBT, IET0-IET2, IE0, IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB15 addr1 (Only in the MKII mode) caddr faddr taddr PORTn IExxx RBn MBn Note mem can be only used for even address in 8-bit data processing. 42 PD753204, 753206, 753208 (2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0 to 3, 5, 6, 8, 9) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : Contents addressed by xx : Hexadecimal data 43 PD753204, 753206, 753208 (3) Explanation of symbols under addressing area column *1 MB = MBE*MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH *2 *3 Data memory addressing *4 *5 *6 PD753204 PD753206 PD753208 addr = 000H-FFFH addr = 0000H-17FFH addr = 0000H-1FFFH *7 addr, addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 PD753204 PD753206 PD753208 caddr = 000H-FFFH caddr = 0000H-0FFFH(PC12 = 0) or 1000H-17FFH(PC12 = 1) caddr = 0000H-0FFFH(PC12 = 0) or 1000H-1FFFH(PC12 = 1) Program memory addressing *9 *10 *11 faddr = 0000H-07FFH taddr = 0020H-007FH PD753204 PD753206 PD753208 addr1 = 000H-FFFH addr1 = 0000H-17FFH addr1 = 0000H-1FFFH Remarks 1. MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instruction Note : S=2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 44 PD753204, 753206, 753208 Number of machine cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B Instruction group Transfer instruction Mnemonic Operand Number of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 Operation Addressing area Skip condition MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA String effect A XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' 45 PD753204, 753206, 753208 Number of machine cycles 3 q Instruction group Table reference Mnemonic Operand Number of bytes 1 Operation Addressing area Skip condition MOVT XA, @PCDE PD753204 XA (PC11-8+DE)ROM q PD753206, 753208 XA (PC12-8+DE)ROM PD753204 XA (PC11-8+XA)ROM PD753206, 753208 XA (PC12-8+XA)ROM XA (BCDE)ROM XA (BCXA)ROM Note XA, @PCXA 1 3 q q XA, @BCDE XA, @BCXA Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA 1 1 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 3 3 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 *6 *6 *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1 Note CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY *1 borrow borrow borrow *1 Note Set "0" to register B if the PD753204 is used. Only the low-order one bit of register B will be valid if the PD753206 or 753208 is used. 46 PD753204, 753206, 753208 Number of machine cycles 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY CY=1 *1 *1 *1 *1 *3 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH reg=n4 (HL) = n4 A = (HL) XA = (HL) A=reg XA=rp' *1 *1 *1 Instruction group Operation Mnemonic Operand Number of bytes 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 Operation Addressing area Skip condition AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation instructions Increment and Decrement instructions RORC NOT INCS A A reg rp1 @HL mem DECS reg rp' Comparison instruction SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulation instruction SET1 CLR1 SKT NOT1 CY CY CY CY 47 PD753204, 753206, 753208 Number of machine cycles 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit) Instruction group Mnemonic Operand Number of bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operation Addressing area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 Skip condition Memory bit SET1 manipulation instructions mem.bit fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit 48 PD753204, 753206, 753208 Number of machine cycles - Instruction group Branch instructions Mnemonic Operand Number of bytes - Operation Addressing area *6 Skip condition BR Note addr * PD753204 PC11-0 addr Select the most appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. * PD753206, 753208 PC12-0 addr Select the most appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. addr1 - - * PD753204 PC11-0 addr1 Select the most appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. * PD753206, 753208 PC12-0 addr1 Select the most appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 ! addr 3 3 * PD753204 PC11-0 addr * PD753206, 753208 PC12-0 addr *6 $addr 1 2 * PD753204 PC11-0 addr * PD753206, 753208 PC12-0 addr *7 $addr1 1 2 * PD753204 PC11-0 addr1 * PD753206, 753208 PC12-0 addr1 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 49 PD753204, 753206, 753208 Number of machine cycles 3 Instruction group Branch instruction Mnemonic Operand Number of bytes 2 Operation Addressing area Skip condition BR PCDE * PD753204 PC11-0 PC11-8+DE * PD753206, 753208 PC12-0 PC12-8+DE PCXA 2 3 * PD753204 PC11-0 PC11-8+XA * PD753206, 753208 PC12-0 PC12-8+XA BCDE 2 3 * PD753204 PC11-0 BCDE *6 Note 1 * PD753206, 753208 PC12-0 BCDE Note 2 BCXA 2 3 * PD753204 PC11-0 BCXA Note 1 * PD753206, 753208 PC12-0 BCXA Note 2 *6 BRA Note 3 !addr1 3 3 * PD753204 PC11-0 addr1 * PD753206, 753208 PC12-0 addr1 *6 BRCB !caddr 2 2 * PD753204 PC11-0 caddr11-0 * PD753206, 753208 PC12-0 PC12+caddr11-0 *8 Subroutine stack control instructions CALLA Note 3 !addr1 3 3 * PD753204 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr1, SP SP-6 * PD753206, 753208 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 PC12-0 addr1, SP SP-6 *11 Notes 1. "0" must be set to the B register. 2. Only the low-order one bit is valid in the B register. 3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 50 PD753204, 753206, 753208 Number of machine cycles 3 Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes 3 Operation Addressing area *6 Skip condition CALL Note !addr * PD753204 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 addr, SP SP-4 * PD753206, 753208 (SP-3) MBE, RBE, 0, PC12 (SP-4) (SP-1) (SP-2) PC11-0 PC12-0 addr, SP SP-4 4 * PD753204 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr, SP SP-6 * PD753206, 753208 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 PC12-0 addr, SP SP-6 CALLF Note !faddr 2 2 * PD753204 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 0+faddr, SP SP-4 * PD753206, 753208 (SP-3) MBE, RBE, 0, PC12 (SP-4) (SP-1) (SP-2) PC11-0 PC12-0 00+faddr, SP SP-4 *9 3 * PD753204 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 0+faddr, SP SP-6 * PD753206, 753208 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 PC12-0 00+faddr, SP SP-6 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 51 PD753204, 753206, 753208 Number of machine cycles 3 Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes 1 Operation Addressing area Skip condition RET Note * PD753204 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 * PD753206, 753208 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, PC12 (SP+1), SP SP+4 * PD753204 x, x, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC11-0 (SP) (SP+3) (SP+2), SP SP+6 * PD753206, 753208 x, x, MBE, RBE (SP+4) MBE, 0, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2), SP SP+6 RETS Note 1 3+S MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally * PD753204 Unconditional * PD753206, 753208 MBE, RBE, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally * PD753204 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally * PD753206, 753208 0, 0, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+4 then skip unconditionally Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 52 PD753204, 753206, 753208 Number of machine cycles 3 Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes 1 Operation Addressing area Skip condition RETI Note 1 * PD753204 MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 * PD753206, 753208 MBE, RBE, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 * PD753204 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 * PD753206, 753208 0, 0, 0, PC12 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PUSH rp BS 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1) (SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n (n = 0-3) (n = 0, 1, 15) (n = 0-3, 5, 6, 8, 9) (n = 8) (n = 3, 5, 6, 8, 9) (n = 8) POP rp BS Interrupt control instructions EI IExxx DI IExxx 2 2 2 2 2 2 2 2 2 1 Input/output instructions IN Note 2 A, PORTn XA, PORTn OUT Note 2 PORTn, A PORTn, XA CPU control instructions HALT STOP NOP Special instructions SEL RBn MBn 2 2 Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 53 PD753204, 753206, 753208 Instruction group Special instructions Number of bytes 1 Number of machine cycles 3 Addressing area *10 Mnemonic Operand Operation Skip condition GET Notes 1, 2 taddr * PD753204 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) ---------------------------------- ------------- * When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr) 3-0 + (taddr+1) SP SP-4 ---------------------------------- ------------- * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction * PD753206, 753208 * When TBR instruction PC12-0 (taddr) 4-0 + (taddr+1) ---------------------------------- ------------- * When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 (taddr) 4-0 + (taddr+1) SP SP-4 ---------------------------------- ------------- * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 Depending on the reference instruction *10 * PD753204 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) * When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC11-0 (taddr) 3-0 + (taddr+1) SP SP-6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- ------------- 4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- ------------- 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 2. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 54 PD753204, 753206, 753208 Instruction group Special instructions Number of bytes 1 Number of machine cycles 3 Addressing area *10 Mnemonic Operand Operation Skip condition GETI Notes 1, 2 taddr * PD753206, 753208 * When TBR instruction PC12-0 (taddr) 4-0 + (taddr+1) * When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, PC12 (SP-2) x, x, MBE, RBE PC12-0 (taddr) 4-0 + (taddr+1) SP SP-6 ------------------------------------- ---- ------------- 4 ------------------------------------- ---- ------------- 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 2. The above operations in the double boxes can be performed only in the Mk II mode. 55 PD753204, 753206, 753208 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Except port 5 Port 5 On-chip pull-up resistor When N-ch open-drain Output voltage Output current high VO IOH Per pin Total for all pins Output current low IOL Per pin Total for all pins Operating ambient temperature Storage temperature TA Test Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85 Note Unit V V V V V mA mA mA mA C Tstg -65 to +150 C Note When LCD is driven in normal mode: TA = -10 to +85C Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. CAPACITANCE (TA = 25C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 56 PD753204, 753206, 753208 SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator C1 VDD Recommended constant X1 X2 Parameter Oscillator frequency (fX) Note 1 Test conditions MIN. 1.0 TYP. MAX. 6.0 Note 2 Unit MHz C2 Oscillation stabilization time Note 3 Oscillator frequency (fX) Note 1 After VDD reaches oscillation voltage range MIN. 1.0 6.0 4 ms Crystal resonator C1 X1 X2 Note 2 MHz C2 VDD Oscillation stabilization time Note 3 X1 input frequency (fX) Note 1 X1 input high/low level width (tXH, tXL) VDD = 4.5 to 5.5 V 10 30 1.0 6.0 Note 2 ms External clock MHz X1 X2 83.3 500 ns Notes 1. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the instruction execution time, refer to the AC characteristics. 2. When the oscillator frequency is 4.19 MHz < fx 6.0 MHz, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required 0.95 s. Therefore, set PCC to a value other than 0011. 3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VDD. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 57 PD753204, 753206, 753208 RECOMMENDED OSCILLATOR CONSTANTS Ceramic resonator (TA = -40 to 85C) Manufacturer TDK Part number CCR1000K2 CCR2.0MC33 CCR3.58MC3 CCR4.19MC3 FCR4.19MC5 CCR6.0MC3 FCR6.0MC5 6.0 2.5 Frequency (MHz) 1.0 2.0 3.58 4.19 2.2 Oscillator constant (pF) C1 100 -- C2 100 -- Oscillation voltage range (VDD) MIN. (V) 1.8 2.0 MAX. (V) 5.5 -- On-chip capacitor Remark Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillaiton frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 58 PD753204, 753206, 753208 DC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Output voltage low Symbol IOL Per pin Sum of the all pins Input voltage high VIH1 Ports 2, 3, 8, and 9 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH3 Port 5 When a pull-up register 2.7 VDD 5.5 V is incorporated 1.8 VDD < 2.7 V When N-ch open-drain 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH4 Input voltage low VIL1 X1 Ports 2, 3, 5, 8, and 9 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL3 Output voltage high Output voltage low VOH VOL1 X1 SCK, SO, ports 2, 3, 6, 8, and 9 IOH = -1.0 mA SCK, SO, ports 2, 3, 5, 6, 8, and 9 IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 Input leakage current high ILIH1 ILIH2 ILIH3 Input leakage current low ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V SB0, SB1 VIN = VDD N-ch open-drain pull-up resistor 1 k Other pins than X1 X1 Port 5 (When N-ch open-drain) Other pins than port 5 and X1 X1 Port 5 (When N-ch open drain) Other than when an input instruction is executed Port 5 (When N-ch open-drain) When an input instruction VDD = 5.0 V is executed VDD = 3.0 V Output leakage current high ILOH1 VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 8 and 9 Port 5 (When a pull-up resistor is incorporated.) Port 5 (When N-ch open-drain) 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD 0.7VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 0.2 2.0 0.4 0.2VDD 3 20 20 -3 -20 -3 Test conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V V V A A A A A A -30 -10 -3 -27 -8 3 A A A A ILOH2 Output leakage current low On-chip pull-up resistor ILOL RL1 RL2 VOUT = 13 V VOUT = 0 V VIN = 0 V 20 -3 A A k k Ports 0 to 3, 6, 8, and 9 (Excluding P00 pin) Port 5 (Mask option) 50 15 100 30 200 60 59 PD753204, 753206, 753208 DC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD VAC0 = 0 Test conditions TA = -40 to +85C TA = -10 to +85C VAC0 = 1 VAC current Note 1 Note 2 MIN. 2.7 2.2 1.8 TYP. MAX. VDD VDD VDD Unit V V V IVAC RLCD1 RLCD2 VAC0 = 1, VDD = 2.0 V 10% 50 5 lO = 1.0 A lO = 0.5 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 1.8 V VLCD VDD 0 1 100 10 4 200 20 0.2 0.2 A k k V LCD split resistor LCD output voltage deviation Note 3 (common) VODC LCD output voltage VODS deviation Note 3 (segment) Supply current Note 4 IDD1 0 V IDD2 6.0 MHz VDD = 5.0 V 10% Note 5 Crystal oscillation VDD = 3.0 V 10% Note 6 C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% 1.9 0.4 0.72 0.27 1.5 0.25 0.7 0.23 0.05 0.02 6.0 1.3 2.1 0.8 4.0 0.75 2.0 0.7 10 5 3 mA mA mA mA mA mA mA mA IDD1 IDD2 4.19 MHz VDD = 5.0 V 10% Note 5 Crystal oscillation VDD = 3.0 V 10% Note 6 C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% IDD3 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% A A A TA = 25C 0.02 Notes 1. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1 A. 2. Either RLCD1 or RLCD2 can be selected by the mask option. 3. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). 4. Not including currents flowing in on-chip pull-up resistors or LCD split resistors. 5. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. 6. When PCC is set to 0000 and the device is operated in the low-speed mode. 60 PD753204, 753206, 753208 AC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter CPU clock cycle time Note 1 TI0 input frequency Symbol tCY VDD = 2.7 to 5.5 V Test conditions MIN. 0.67 0.95 fTI VDD = 2.7 to 5.5 V 0 0 TI0 input high/low-level width Interrupt input high/ low-level width tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 tINTH, tINTL INT0 IM02 = 0 IM02 = 1 INT4 KR0 to KR3 RESET low level width tRSL Note 2 TYP. MAX. 64 64 1.0 275 Unit s s MHz kHz s s s s s s s 10 10 10 10 Notes 1. The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic. 2. 2tCY or 128/fX is set by setting the interrupt mode register (IM0). 1 Cycle Time tCY [ s] 6 5 4 3 64 30 tCY vs VDD clock) and the processor clock Guaranteed Operation Range 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 61 PD753204, 753206, 753208 SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high/low-level width SINote 1 setup time (to SCK) SI Note 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKL1, tKH1 VDD = 2.7 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 150 tSIK1 VDD = 2.7 to 5.5 V 150 500 hold time tKSI1 VDD = 2.7 to 5.5 V 400 600 (from SCK) SONote 1 output delay time from SCK tKSO1 RL = 1 k, CL = 100 pF Note 2 VDD = 2.7 to 5.5 V 0 0 250 1000 ns ns Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL are the load resistance and load capacitance of the SO output lines. 2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high/low-level width SINote 1 setup time (to SCK) SI Note 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKL2, tKH2 VDD = 2.7 to 5.5 V 400 1600 tSIK2 VDD = 2.7 to 5.5 V 100 150 hold time tKSI2 VDD = 2.7 to 5.5 V 400 600 (from SCK) SONote 1 output delay time from SCK tKSO2 RL = 1 k, CL = 100 pF Note 2 VDD = 2.7 to 5.5 V 0 0 300 1000 ns ns Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL are the load resistance and load capacitance of the SO output lines. 62 PD753204, 753206, 753208 SBI Mode (SCK...Internal clock output (master)): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high/low-level width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tSIK3 VDD = 2.7 to 5.5 V tKL3, tKH3 VDD = 2.7 to 5.5 V tKCY3/2 - 50 tKCY3/2 - 150 150 500 tKSI3 VDD = 2.7 to 5.5 V tKCY3/2 TYP. MAX. Unit ns ns ns ns ns ns ns tKSO3 RL = 1 k, CL = 100 pF Note VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines. SBI Mode (SCK...External clock input (slave)): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high/low-level width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tSIK4 VDD = 2.7 to 5.5 V tKL4, tKH4 VDD = 2.7 to 5.5 V 400 1600 100 150 tKSI4 VDD = 2.7 to 5.5 V tKCY4/2 TYP. MAX. Unit ns ns ns ns ns ns ns tKSO4 RL = 1 k, CL = 100 pF Note VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines. 63 PD753204, 753206, 753208 AC Timing Test Point (Excluding X1 Input) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock Timing 1/fX tXL tXH X1 Input VDD-0.1 V 0.1 V TI0 Timing 1/fTI tTIL tTIH TI0 64 PD753204, 753206, 753208 Serial Transfer Timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SI tKSO1, 2 Input Data SO Output Data 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 65 PD753204, 753206, 753208 Serial Transfer Timing Bus release signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INTP0, 4 KR0 to 3 RESET input timing tRSL RESET 66 PD753204, 753206, 753208 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85C) Parameter Release signal set time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Release by RESET Release by interrupt Test conditions MIN. 0 Note 2 Note 3 TYP. MAX. Unit s ms ms Notes 1. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 2. Either 2 17/fX or 215/fX can be selected by the mask option. 3. Depends on the basic interval timer mode register (BTM) settings (See the table below). BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Wait When fx = 4.19-MHz operation 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.81 ms) 213/fX (approx. 1.95 ms) time When fx = 6.0-MHz operation 220/fX (approx. 175 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.37 ms) Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation Halt mode STOP Mode Operating Mode Data Retention Mode VDD tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) Halt mode STOP Mode Operating Mode Data Retention Mode VDD tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 67 PD753204, 753206, 753208 13. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs VDD (System Clock : 6.0-MHz Crystal Resonator) (TA = 25 C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode Supply Current IDD (mA) 0.5 0.1 0.05 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF VDD 0.01 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 68 PD753204, 753206, 753208 IDD vs VDD (System Clock : 4.19-MHz Crystal Resonator) (TA = 25C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode Supply Current IDD (mA) 0.5 0.1 0.05 X1 X2 Crystal resonator 4.19 MHz 22 pF 22 pF VDD 0.01 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 69 PD753204, 753206, 753208 14. PACKAGE DRAWINGS 48 PIN PLASTIC SHRINK SOP (375 mil) 48 25 detail of lead end 1 A 24 H G 3+7 -3 I J F C D MM N B E K L P48GT-65-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 16.21 MAX. 0.63 MAX. 0.65 (T.P.) 0.30 0.10 0.125 0.075 2.0 MAX. 1.7 0.1 10.0 0.3 8.0 0.2 1.0 0.2 0.15+0.10 -0.05 0.5 0.2 0.10 0.10 INCHES 0.639 MAX. 0.025 MAX. 0.026 (T.P.) 0.012+0.004 -0.005 0.005 0.003 0.079 MAX. 0.067 0.004 0.394 +0.012 -0.013 0.315 0.008 0.039+0.009 -0.008 0.006+0.004 -0.002 0.020+0.008 -0.009 0.004 0.004 70 PD753204, 753206, 753208 15. RECOMMENDED SOLDERING CONDITIONS The PD753208 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions PD753204GT-xxx PD753206GT-xxx PD753208GT-xxx Soldering Method Infrared rays reflow VPS : 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) : 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) : 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) Soldering Conditions Peak package's surface temperature: 235C, Reflow time: 30 seconds or less (at 210C or higher), Number of reflow processes: Twice max. Peak package's surface temperature: 215C, Reflow time: 40 seconds or less (at 200C or higher), Number of reflow processes: Twice max. Solder temperature: 260C or below, Flow time: 10 seconds or less, Number of flow process: 1, Preheating temperature: 120C or below (Package surface temperature) Pin temperature: 300C or below, Time: 3 seconds or less (per device side) Symbol IR35-00-2 VP15-00-2 Wave soldering WS60-00-1 Partial heating -- Caution Use of more than one soldering method should be avoided (except for partial heating). 71 PD753204, 753206, 753208 APPENDIX A PD753108, 753208, AND 75P3216 FUNCTIONAL LIST Parameter Program memory PD753108 Mask ROM 0000H-1FFFH (8192 x 8 bits) PD753208 PD75P3216 One-time PROM 0000H-3FFFH (16384 x 8 bits) Data memory 000H-1FFH (512 x 4 bits) 75XL CPU When main system clock is selected When subsystem clock is selected * 0.95, 1.91, 3.81, 15.3 s (@ 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0-MHz operation) 122 s (@ 32.768-kHz operation) 8 (on-chip pull-up resistors can be specified by software: 7) None CPU Instruction execution time I/O port CMOS input 6 (on-chip pull-up resistors can be specified by software: 5) CMOS input/output N-ch open drain input/output Total LCD controller/driver 20 (on-chip pull-up resistors can be specified by software) 4 (on-chip pull-up resistors can be specified by software, withstand voltage is 13 V) 32 Segment selection: 16/20/24 (can be changed to CMOS input/output port in 4 timeunit; max. 8) 30 Segment selection: 4/8/12 segments (can be changed to CMOS input/output port in 4 time-unit; max. 8) 4 (no mask option, withstand voltage is 13 V) Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option. Timer 5 channels * 8-bit timer/event counter: 3 channels * Basic interval timer/ watchdog timer: 1 channel * Watch timer: 1 channel No on-chip split resistor for LCD driver 5 channels * 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier generator, and timer with gate) * 8-bit timer/event counter: 1 channel * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel Clock output (PCL) * , 524, 262, 65.5 kHz (Main system clock: @ 4.19-MHz operation) * , 750, 375, 93.8 kHz (Main system clock: @ 6.0-MHz operation) * 2, 4, 32 kHz (Main system clock: @ 4.19-MHz operation or subsystem clock: @ 32.768-kHz operation) * 2.86, 5.72, 45.8 kHz (Main system clock: @ 6.0-MHz operation) 3 * * * * 2, 4, 32 kHz (Main system clock: @ 4.19-MHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: @ 6.0-MHz operation) Buzzer output (BUZ) Serial interface modes are available 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit 2-wire serial I/O mode SBI mode None SCC register SOS register Vectored interrupt Contained External: 3, internal: 5 External: 2, internal: 5 72 PD753204, 753206, 753208 Parameter Test input Operation supply voltage Operating ambient temperature Package PD753108 External: 1, internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic QFP (12 x 12 mm) PD753208 PD75P3216 * 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 73 PD753204, 753206, 753208 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the PD753208. In 75XL series, the relocatable assembler which is common to the PD753208 Subseries is used in combination with the device file of each product. Language processor RA75X relocatable assembler Host machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2 IBM PC/AT TM and compatible machines Note Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name) S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X Refer to section "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Device file Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Note Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name) S5A13DF753208 S5A10DF753208 S7B13DF753208 S7B10DF753208 Refer to section "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC PROM write tools Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcomputers including PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256 Kbits to 4 Mbits. PROM programmer adapter for the PD75P3216GT. Connect the programmer adapter to PG-1500 for use. PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Note PA-75P3216GT Software PG-1500 controller Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name) S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 Refer to section "OS for IBM PC" 3.5-inch 2HD 5-inch 2HC Note Ver. 5.00 or later have the task swap function, but it cannot be used for this software. Remarks 1. Operation of the assembler and device file is guaranteed only on the above host machine and OSs. 2. Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs. 74 PD753204, 753206, 753208 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the PD753208. The system configurations are described as follows. Hardware IE-75000-R Note 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP753208GT-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP753208GT-R which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. Emulation board for evaluating the application systems that use a PD753208 subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD753208GT. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 48-pin conversion adapter EV-9500GF-48 which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and its compatible machine Note 2 IE-75001-R IE-75300-R-EM EP-753208GT-R EV-9500GF-48 Software IE control program Distribution media 3.5-inch 2HD 5-inch 2HD Part No. (product name) S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Refer to section "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Notes 1. Maintenance parts. 2. Ver. 5.00 or later have the task swap function, but it cannot be used for this software. Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs. 2. The PD753204, 753206, 753208, and 75P3216 are commonly referred to as the PD753208 Subseries. 75 PD753204, 753206, 753208 OS for IBM PC The following IBM PC OS's are supported. OS PC DOS TM Version Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note J5.02/V Note MS-DOS IBM DOS TM Note English version is supported. Ver. 5.0 and later have the task swap function, but it cannot be used for this software. Caution 76 PD753204, 753206, 753208 APPENDIX C RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to device Document No. Document Name Japanese English This manual U10241E U10158E U10453E PD753204, 753206, 753208 Data Sheet PD75P3216 Data Sheet PD753208 User's Manual 75XL Series Selection Guide U10166J U10241J U10158J U10453J Documents related to development tool Document No. Document Name Japanese Hardware IE-75000-R/IE-75001-R User`s Manual IE-75300-R-EM User's Manual EP-753208GT-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual PC-9800 Series (MS-DOS) Base IBM PC Series (PC DOS) Base EEU-846 U11354J U10739J U11940J EEU-731 EEU-730 EEU-704 EEU-5008 English EEU-1416 U11354E U10739E EEU-1335 EEU-1346 EEU-1363 EEU-1291 U10540E Other related documents Document No. Document Name Japanese Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcontroller - Related Product Guide - Third Party Products - C10943X C10535J C11531J C10983J MEM-539 C11893J C11416J C10535E C11531E C10983E IEI-1201 MEI-1202 - English Caution The contents of the documents listed above are subject to change without prior notice to users. Make sure to use the latest edition when starting design. 77 PD753204, 753206, 753208 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 78 PD753204, 753206, 753208 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 79 PD753204, 753206, 753208 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 80 |
Price & Availability of UPD753206
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